DC-Link Capacitance Minimization in T-Type Three-Level AC/DC/AC PWM Converters

Title
DC-Link Capacitance Minimization in T-Type Three-Level AC/DC/AC PWM Converters
Author(s)
이동춘알레미파얌정윤철
Keywords
MULTILEVEL CONVERTERS; INVERTER; DESIGN; STRATEGY
Issue Date
201503
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, v.62, no.3, pp.1382 - 1391
Abstract
In this paper, a novel control algorithm that minimizes the dc-link capacitance in the T-type three-level back-to-back converter is proposed. For this, the charging and discharging currents through the capacitor should be minimized, which can be achieved by utilizing the power balance of the ac/dc converter. Then, the voltage variation in the dc-link is also decreased, which makes a significant reduction in the size of dc-link capacitors. With this scheme, the electrolytic capacitors can be replaced by film capacitors, which are of higher power density, longer lifetime, and higher reliability. The effectiveness of the proposed strategy has been verified by the simulation and experiment results for a 3-kW T-type three-level ac/dc/ac pulsewidth modulation converter system with a 50-mu F film capacitor in the dc-link.
URI
http://hdl.handle.net/YU.REPOSITORY/33230http://dx.doi.org/10.1109/TIE.2014.2345354
ISSN
0278-0046
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공과대학 > 전기공학과 > Articles
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