Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects

Title
Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects
Author(s)
안병철S.Kannan[S.Kannan]Bruce Kim[Bruce Kim]
Issue Date
201202
Publisher
SPRINGER
Citation
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, v.28, no.1, pp.39 - 51
Abstract
This paper provides a new test technique for detecting defects in Through Silicon Via (TSV) in 3-D ICs and presents a substrate-dependent equivalent electrical model for TSVs. Process-related defects that affect the functional electrical performance of the TSV are identified, and fault models are developed for each individual defect. The fault models are integrated into the equivalent electrical model of the TSV for testing. Our test technique uses an RF carrier signal modulated with a multi-tone signal with added Gaussian white noise to synthesize the test stimulus; the peak-to-average ratio is measured as output response. We find a significant difference in peak-to-average ratio between defect-free and defective TSVs. Our test technique is very sensitive to small defects in these nanostructures, thereby identifying the defects with high accuracy.
URI
http://hdl.handle.net/YU.REPOSITORY/29951http://dx.doi.org/10.1007/s10836-011-5263-2
ISSN
0923-8174
Appears in Collections:
공과대학 > 컴퓨터공학과 > Articles
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