Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Mulltiprocessors

Title
Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Mulltiprocessors
Author(s)
곽종욱엄영식[엄영식]장성태[장성태]전주식[전주식]
Issue Date
201206
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E95D, no.6, pp.1676 - 1679
Abstract
In Chip Multi-Processors (CMPs), private L2 caches have potential benefits in future CMPs, e.g. small access latency, performance isolation, tile-friendly architecture and simple low bandwidth on-chip interconnect. But the major weakness of private cache is the higher cache miss rate caused by small private cache capacity. To deal with this problem, private caches can share capacity through spilling replaced blocks to other private caches. However, indiscriminate spilling can make capacity problem worse and influence performance negatively. This letter proposes throttling capacity sharing (TCS) for effective capacity sharing in private L2 caches. TCS determines whether to spill a replaced block by predicting reuse possibility, based on life time and reuse time. In our performance evaluation, TCS improves weighted speedup by 48.79%, 6.37% and 5.44% compared to non-spilling, Cooperative Caching with best spill probability (CC) and Dynamic Spill-Receive (DSR), respectively.
URI
http://hdl.handle.net/YU.REPOSITORY/28073http://dx.doi.org/10.1587/transinf.E95.D.1676
ISSN
0916-8532
Appears in Collections:
공과대학 > 컴퓨터공학과 > Articles
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