A Superscalar software architecture model for Multi-Core Processors (MCPs)

Title
A Superscalar software architecture model for Multi-Core Processors (MCPs)
Author(s)
최규상Chita R. Das[Chita R. Das]
Issue Date
201007
Publisher
ELSEVIER SCIENCE INC
Citation
JOURNAL OF SYSTEMS AND SOFTWARE, v.83, no.10, pp.1823 - 1837
Abstract
Design of high-performance servers has become a research thrust to meet the increasing demand of network-based applications. One approach to design such architectures is to exploit the enormous computing power of Multi-Core Processors (MCPs) that are envisioned to become the state-of-the-art in processor architecture. In this paper, we propose a new software architecture model. called SuperScalar, suitable for MCP machines. The proposed SuperScalar model consists of multiple pipelined thread pools, where each pipelined thread pool consists of multiple threads, and each thread takes a different role. The main advantages of the proposed model are global information sharing by the threads and minimal memory requirement due to fewer threads. We have conducted in-depth performance analyses of the proposed scheme along with three prior software architecture schemes (Multi-Process (MP), Multi-Thread (MT) and Event-Driven (ED)) via an analytical model. The performance results indicate that the proposed SuperScalar model shows the best performance across all system and workload parameters compared to the MP, MT and ED models. Although the MT model shows competitive performance with less number of processing cores and smaller data cache size, the advantage of the SuperScalar model becomes obvious as the number of processing cores increases. (C) 2010 Elsevier Inc. All rights reserved.
URI
http://hdl.handle.net/YU.REPOSITORY/23921http://dx.doi.org/10.1016/j.jss.2010.04.068
ISSN
0164-1212
Appears in Collections:
공과대학 > 모바일정보통신공학과 > Articles
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