Compressed tag architecture for low-power embedded cache systems

Title
Compressed tag architecture for low-power embedded cache systems
Author(s)
곽종욱전영태[전영태]
Keywords
PARTIAL RESOLUTION
Issue Date
201009
Publisher
ELSEVIER SCIENCE BV
Citation
JOURNAL OF SYSTEMS ARCHITECTURE, v.56, no.9, pp.419 - 428
Abstract
Processors in embedded systems mostly employ cache architectures in order to alleviate the access latency gap between processors and memory systems. Caches in embedded systems usually occupy a major fraction of the implemented chip area. The power dissipation of cache system thus constitutes a significant fraction of the power dissipated by the entire processor in embedded systems. In this paper, we propose the compressed tag architecture to reduce the power dissipation of the tag store in cache systems. We introduce a new tag-matching mechanism by using a locality buffer and a tag compression technique. The main power reduction feature of our proposal is the use of small tag space matching instead of full tag matching, with modest additional hardware costs. The simulation results show that the proposed model provides a power and energy-delay product reduction of up to 27.8% and 26.5%, respectively, while still providing a comparable level of system performance to regular cache systems. (C) 2010 Elsevier B.V. All rights reserved.
URI
http://hdl.handle.net/YU.REPOSITORY/23704http://dx.doi.org/10.1016/j.sysarc.2010.04.010
ISSN
1383-7621
Appears in Collections:
공과대학 > 컴퓨터공학과 > Articles
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