Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

Title
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)
Author(s)
곽종욱경현민[경현민]박기호[박기호]김태진[김태진]박성배[박성배]
Issue Date
201006
Publisher
ELSEVIER SCIENCE BV
Citation
MICROPROCESSORS AND MICROSYSTEMS, v.34, no.2-4, pp.102 - 116
Abstract
With the rapid development of semiconductor technology, more complicated systems have been integrated into single chips However, system performance is not increased in proportion to the gate-count of the system. This is mainly because the optimized design of the system becomes more difficult as the systems become more complicated Therefore, it is essential to understand the internal behavior of the system and utilize the system resources effectively in the System on Chip (SOC) design. In this paper, we design a Performance Analysis Unit (PAU) for monitoring the AMBA Advanced eXtensible Interface (AXI) bus as a mechanism to investigate the internal and dynamic behavior of an SOC, especially for internal bus activities A case study with the PAU for an H 264 decoder application is also presented to show how the PAU is utilized in SOC platform. The PAU has the capability to measure major system performance metrics, such as bus latency, amount of bus traffic, contention between master/slave devices, and bus utilization for specific durations This paper also presents a distributor and synchronization method to connect multiple PAUs to monitor multiple internal buses of large SOC (C) 2010 Elsevier B.V. All rights reserved
URI
http://hdl.handle.net/YU.REPOSITORY/22362http://dx.doi.org/10.1016/j.micpro.2010.03.001
ISSN
0141-9331
Appears in Collections:
공과대학 > 컴퓨터공학과 > Articles
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