Automatic Defect Classification System in Semiconductors EDS Test Based on System Entity Structure Methodology

Title
Automatic Defect Classification System in Semiconductors EDS Test Based on System Entity Structure Methodology
Author(s)
한영신[한영신]김소영[김소영]김태규[김태규]정재은
Issue Date
201007
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E93D, no.7, pp.2001 - 2004
Abstract
We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.
URI
http://hdl.handle.net/YU.REPOSITORY/22176http://dx.doi.org/10.1587/transinf.E93.D.2001
ISSN
0916-8532
Appears in Collections:
공과대학 > 컴퓨터공학과 > Articles
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